1. Technical Field
Various embodiments generally relate to an integrated circuit, and more particularly to a sense amplifier driving device for stabilizing a bit line precharge power when a post-overdriving operation is performed.
2. Related Art
Demands for high-speed, highly integrated semiconductor memory devices are leading to advances in synchronous memory devices. The synchronous memory device has an interface that is synchronized with the system bus.
A single data rate (hereinafter referred to as “SDR”) synchronous memory device transfers only one data bit per clock cycle of the system bus. The SDR synchronous memory device transfers a data bit on either the rising edge or the falling edge of the clock.
However, the SDR synchronous memory device is still insufficient to satisfy speed requirements of a system. A double data rate (“DDR”) synchronous memory device is faster than the SDR synchronous memory device. The DDR synchronous memory device transfers data bits on both the rising and falling edges of the clock signal.
Each of the data input/output pins of the DDR synchronous memory device continuously inputs and outputs two data in synchronization with the rising edge and falling edge of an external clock (e.g. system clock). Accordingly, without increasing clock frequency, the DDR synchronous memory device can input/output data at higher speed than the SDR synchronous memory device because the bandwidth of the DDR synchronous memory device is at least twice the bandwidth of the SDR synchronous memory device.
Dynamic random access memory (“DRAM”) is a volatile memory device. A memory cell of DRAM includes a cell transistor and a cell capacitor.
The cell transistor functions to transfer electrical charges from the cell capacitor to a bit line, and the cell capacitor stores electrical charges corresponding to data. That is, each data bit may have a high voltage level or a low voltage level depending on the amount of charges stored in the cell capacitor.
A memory cell of DRAM requires a refresh operation, which is the process of periodically reading data from the memory cell and immediately rewriting the read data to the same memory cell.
A memory cell of DRAM is activated in an active mode. A sense amplifier, which is used when data is read from the memory cell, may sense a small voltage level of a data bit, which is read from a memory cell through a bit line, and amplify the small voltage level to recognizable logic levels so the data can be interpreted properly. The bit line sense amplifier circuit may also write back the amplified data on the memory cell.
Furthermore, in a precharge mode, a memory cell is deactivated, and the memory cell retains data. The refresh operation may include an active operation and a precharge operation, which are repeatedly performed in a specific cycle.
When a refresh operation is performed, a post-overdriving operation may be performed to reduce an electric current that will be consumed in the next sensing operation. When a post-overdriving operation mode ends, the level of a bit line precharge voltage rises. In this case, when a precharge operation is performed after the activation operation, it may be difficult for the sense amplifier to sense a high-voltage data bit.